Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

Microstrip Impedance Management through Multilayer PCB Stack-Up: Discontinuity Compensation Voids with Asymmetric Dielectrics

To process high-frequency signals on a printed circuit board (PCB), it is often necessary to carefully analyze and select the pad widths of the chip packages and components to match their impedance to the standard Z0. Modern PCBs are complex multilayer designs, utilizing either only high-end laminates, low-end laminates, or a combination of both. The on-board component footprints usually have larger pads that become discontinuities and corrupt the impedance of critical traces. One way to address this issue is to include reference plane cutouts as a measure of compensation. This paper aims to find out how an asymmetric dielectric stack-up affects the microstrip discontinuity impedance compensation using reference plane cutouts. The selected board layer stack-up imitates several different practical design scenarios, including costly PCBs that strictly comprise high-end dielectric materials, as well as trying to lower PCB cost by introducing low-cost materials without major performance sacrifice. S-parameter measurements are performed and confirmed by time domain reflectometry (TDR) measurements

A Review of Advanced CMOS RF Power Amplifier Architecture Trends for Low Power 5G Wireless Networks

The structure of the modern wireless network evolves rapidly and maturing 4G networks pave the way to next generation 5G communication. A tendency of shifting from traditional high-power tower-mounted base stations towards heterogeneous elements can be spotted, which is mainly caused by the increase of annual wireless users and devices connected to the network. The radio frequency (RF) power amplifier (PA) performance directly affects the efficiency of any transmitter, therefore, the emerging 5G cellular network requires new PA architectures with improved efficiency without sacrificing linearity. A review of the most promising reported RF PA architectures is presented in this article, emphasizing advantages, disadvantages and concluding with a quantitative comparison. The main scope of reviewed papers are PAs implemented in scalable complementary metal–oxide–semiconductor (CMOS) and SiGe BiCMOS processes with output powers suitable for portable wireless devices under 32 dBm (1.5 W) in the low- and high- 5G network frequency ranges.This article belongs to the Section Microwave and Wireless CommunicationsThis research was funded by the Research Council of Lithuania grant number DOTSUT-235, No. 01.2.2-LMT-K-718-01-0054 as a part of “Design and Research of Internet of Things (IoT) Framework Model and Tools for Intelligent Transport Systems” project. The article processing charges (APC) were funded by Vilnius Gediminas technical university Faculty of Electronics

A Methodology Improving Off-Chip, Lumped RF Impedance Matching Network Response Accuracy

Impedance matching is concurrent with any radio frequency (RF) circuit design and is essential for maximizing the gain and efficiency while minimizing the noise of high-frequency amplifiers as well as some mixer topologies. The main impedance matching network components are capacitors, inductors, and RF transformers all of which contain parasitic parameters that influence the matching response S11 curve. After calculating matching network component values using classical matching techniques, the measured and simulated response curves differ depending on the target frequency. This results in multiple calculations and measurement cycles in order to precisely match the source and load at the desired frequency. This article proposes an algorithm and methodology of estimating component parasitic parameters and taking them into account when calculating the main component parameters (capacitance and inductance). The proposed algorithm has been implemented as a toolbox in Cadence Virtuoso and verified through simulation and measurements. Measurement results show, that at 500 MHz 10% tolerance components with parasitics included and values based on classical theory provide a 3.2–9.8% offset from the target frequency. In the same conditions, matching networks with compensated (according to the proposed algorithm) values provide 0.1–8.8% target frequency offset. At 1500 MHz 10% components provided 4–12.3% (non-compensated) and 1–8.7% (compensated) target frequency offset ranges. At 3000 MHz. The frequency offset range of using compensated matching network component values is reduced from 5.5–15.1% to 1.3–8.1%.This research was funded by the Research Council of Lithuania grant number DOTSUT-235, No. 01.2.2-LMT-K-718-01-0054 as a part of “Design and Research of Internet of Things (IoT) Framework Model and Tools for Intelligent Transport Systems” project. The APC was funded by Vilnius Gediminas technical university Faculty of Electronics

Reduced-Reflection Multilayer PCB Microstrip with Discontinuity Characterization

In the era of technology and communication, printed circuit boards (PCBs) can be found in a myriad of devices—from ordinary household items, to state of the art custom metrology equipment. Different types of component for wireless communications are available and come in various packages, supplied by multiple manufacturers. The signal landpads for some high-frequency connectors and components, encapsulated in larger packages, are usually wider than the controlled impedance trace, thereby introducing unwanted impedance mismatch and resulting in signal reflections. The component land pad and microstrip width a discrepancy issue can be found in both complex high-density industrial devices and system-level academic research papers. This paper addresses the topic of compensating discontinuities, introduced by signal pads, which are wider than the target impedance microstrip, characterizes the difference between the compensated and uncompensated microstrip with discontinuity, and proposes a generalized guideline on compensating for the introduced impedance change in multilayer PCBs. The compensation method is based upon carefully designing the stackup of the PCB allowing for a reference plane cutout under the discontinuity to even out the impedance mismatch. A 6-layer PCB with IT180A dielectric material containing three structures has been manufactured and characterized using an Agilent E8363B vector network analyzer (VNA). A 4–12 dB improvement in S11 response in the whole frequency range up to 10 GHz, compared to that when no compensation has been applied, was observedThis article belongs to the Section Circuit and Signal Processin

Design of a 65 nm CMOS comparator with hysteresis

The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator’s circuit. This article presents the results of a CMOS comparator with hysteresis design – the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC. Article in Lithuanian. 65 nm KMOP technologijos histerezinio komparatoriaus projektavimas Santrauka Komparatorius yra vienas iš pagrindinių elektronikos įtaisų. Jis yra naudojamas kaip diskretinis elementas arba kaip viena iš sudėtingesnės sistemos sudedamųjų dalių. Šie įtaisai dažnai veikia elektronikos sistemose, kuriose egzistuoja ne tik informaciją nešantys bei apdorojami signalai, bet ir nepageidautini triukšmo signalai. Siekiant tokiomis sąlygomis užtikrinti patikimą ir efektyvią komparatoriaus veiką, imama taikyti histerezė. Šiame straipsnyje pateikiami TSMC 65 nm KMOP histerezinio komparatoriaus projektavimo rezultatai: aptariama principinė elektrinė schema, pateikiama suprojektuota topologija, jos kompiuterinio modeliavimo rezultatai bei išvados. Šis komparatorius bus naudojamas daugiastandarčio, daugiakanalio siųstuvo-imtuvo grandinėje, nulinio potencialo poslinkio įtampą nustatančiame, lygiagrečios architektūros analoginiame skaitmeniniame keitiklyje (ASK). Reikšminiai žodžiai: KMOP, komparatorius, histerezė, integrinis grandynas, lustas, analoginis skaitmeninis keitiklis

Surface-Mount Zero-Ohm Jumper Resistor Characterization in High-Speed Controlled Impedance Transmission Lines

Zero-ohm resistors, also known as jumpers, are commonly used in early radio frequency (RF) prototypes as they can help engineers identify the most optimal engineering solution for their system or create application-specific hardware configurations in products. One of the key considerations when using zero-ohm jumpers in RF circuits is the potential for signal loss and interference. Every circuit connection creates a small amount of resistance and impedance, eventually adding up over long distances or in complex circuits. This paper proposes a quantitative characterization summary of standard 0201-, 0402-, 0603-, and 0805-size surface-mount package jumpers, as well as lead-free and lead solder wires, in high-frequency applications by means of time domain reflectometry (TDR) and S-parameter measurements. The typical offset from the target 50 Ω impedance was measured to be around 3 Ω, or 5.8% relative to the measured reference value. According to S-parameter measurement results, no visible impact on attenuation was spotted up to 5 GHz compared to the reference S21 curve

A Method of Optimizing Characteristic Impedance Compensation Using Cut-Outs in High-Density PCB Designs

The modern era of technology contains a myriad of high-speed standards and proprietary serial digital protocols, which evolve alongside the microwave and RF realm. The increasing data rate push the requirements for hardware design, including modern printed circuit boards (PCB). One of these requirements for modern high-speed PCB interfaces are a homogenous track impedance all the way from the source to the load. Even though some high-speed interfaces don’t require any external components embedded into the interconnects, there are others which require either passive or active components—or both. Usually, component package land-pads are of fixed size, thus, if not addressed, they create discontinuities and degrade the transmitted signal. To solve this problem, impedance compensation techniques such as reference plane cut-out are employed for multiple case studies covering this topic. This paper presents an original method of finding the optimal cut-out size for the maximum characteristic impedance compensation in high-density multilayer PCB designs, which has been verified via theoretical estimation, computer simulation, and practical measurement results. Track-to-discontinuity ratios of 1:1.75, 1:2.5, and 1:5.0 were selected in order to resemble most practical design scenarios on a 6-layer standard thickness PCB. The measurements and simulations revealed that the compensated impedance saturation occurs at (150–250%) cut-out widths for a 50 Ω microstrip

0.13 μm CMOS Traveling-Wave Power Amplifier with On- and Off-Chip Gate-Line Termination

Broadband amplifiers are essential building blocks used in high data rate wireless, radar, and instrumentation systems, as well as in optical communication systems. Only a traveling-wave amplifier (TWA) provides sufficient bandwidth for broadband applications without reducing modern linearization techniques. TWA requires gate-line and drain-line termination, which can be implemented on- and off-chip. This article compares the performance of identical 0.13 μm CMOS TWAs, differing only in gate-line termination placement. Measurement results revealed that the designed TWAs with on- and off-chip termination have a bandwidth of 10 GHz with a maximum gain of 15 dB and a power-added efficiency (PAE) of 5%–22% in the whole operating frequency range. Placing the gate-line termination off-chip results in an S21 flatness reduction, compared to the gain of a TWA with on-chip termination. Gain fluctuation over frequency is reduced by 4–8 dB when the termination resistor is placed as an external circuit.This article belongs to the Section Computer Science & Engineerin

A Methodology Improving Off-Chip, Lumped RF Impedance Matching Network Response Accuracy

Impedance matching is concurrent with any radio frequency (RF) circuit design and is essential for maximizing the gain and efficiency while minimizing the noise of high-frequency amplifiers as well as some mixer topologies. The main impedance matching network components are capacitors, inductors, and RF transformers all of which contain parasitic parameters that influence the matching response S11 curve. After calculating matching network component values using classical matching techniques, the measured and simulated response curves differ depending on the target frequency. This results in multiple calculations and measurement cycles in order to precisely match the source and load at the desired frequency. This article proposes an algorithm and methodology of estimating component parasitic parameters and taking them into account when calculating the main component parameters (capacitance and inductance). The proposed algorithm has been implemented as a toolbox in Cadence Virtuoso and verified through simulation and measurements. Measurement results show, that at 500 MHz 10% tolerance components with parasitics included and values based on classical theory provide a 3.2–9.8% offset from the target frequency. In the same conditions, matching networks with compensated (according to the proposed algorithm) values provide 0.1–8.8% target frequency offset. At 1500 MHz 10% components provided 4–12.3% (non-compensated) and 1–8.7% (compensated) target frequency offset ranges. At 3000 MHz. The frequency offset range of using compensated matching network component values is reduced from 5.5–15.1% to 1.3–8.1%